Title:
FOUR-QUADRANT MULTIPLICATION CIRCUIT AND FM RECEIVER HAVING THIS CIRCUIT
Document Type and Number:
Japanese Patent JP3429840
Kind Code:
B2
Abstract:
PURPOSE: To provide a four-quadrant multiplication circuit of a high dynamic range which can be operated with a low supply voltage and has no restrictions caused by the use of a PNP transistor TR.
CONSTITUTION: The four-quadrant multiplication circuit is provided with a dual mutual conductance amplification circuit TAC consisting of NPN TRs 20 to 23 and 64 to 67 coupled to a first input port 36, first and second double Darlington circuits 57 and 58, and a resistance element 78. Darlington circuits 57 and 58 are provided with first NPN TRs 68 and 69, second NPN TRs 70 and 71, and third PNP TRs 72 and 73 respectively. The emitter currents of dual mutual conductance amplifiers are supplied from emitter currents of second TRs 70 and 71 by current mirror circuits 80 and 81.
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Inventors:
Anthony Richard Kasdin
Paul Anthony Moore
Paul Anthony Moore
Application Number:
JP6856694A
Publication Date:
July 28, 2003
Filing Date:
April 06, 1994
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H03D3/06; G06G7/163; H03D3/00; H03D7/14; H03D9/00; H04B1/26; (IPC1-7): H03D3/06; G06G7/163; H03D7/14; H03D9/00; H04B1/26
Domestic Patent References:
| JP5129836A | ||||
| JP18706A | ||||
| JP5338250A | ||||
| JP6120810A |
Attorney, Agent or Firm:
Kosugi Sugimura (4 others)