Title:
FUNCTION MACRO AND ITS DESIGH METHOD, AND SEMICONDUCTOR DEVICE DESIGN METHOD
Document Type and Number:
Japanese Patent JP3651654
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To allow connection at a high freedom level in wiring, without violating a design rule, related to connection with other cells.
SOLUTION: A function macro 2 comprises wiring layers 5 and 6 of two or more layers allocated in a connection pin region 1, and a via contact 4 allocated in a region except for a region (contact inhibited region) 3 which is extended from the connection region 1 and the end part of the connection pin region 1 by a specified distance determined by a design rule. Related to connection to other cells such as a random logic 20, a violation in the design rule is avoided from occurring between a via contact of the random logic 20 and the via contact 4 of the function macro 2.
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Inventors:
Ajimoto Kenichiro
Takehiko Kitajo
Takehiko Kitajo
Application Number:
JP6750899A
Publication Date:
May 25, 2005
Filing Date:
March 12, 1999
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/04; G06F17/50; H01L21/00; H01L21/82; H01L21/822; H01L27/00; (IPC1-7): H01L21/82; G06F17/50; H01L21/822; H01L27/04
Domestic Patent References:
| JP10308452A | ||||
| JP6120224A |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu