Title:
LEVEL CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JP3565922
Kind Code:
B2
Abstract:
PURPOSE: To convert a CMOS level to a shifted ECL level by using a CMOS level converting circuit for converting the voltage level between the CMOS level and the shifted ECL level.
CONSTITUTION: Inside a converting circuit 104, a pFET 106 is connected between a VDD 116 and an output 122, an nFET 108 is connected between the output 122 and a circuit ground 118, and an input to the circuit is a CMOS level voltage connected to the gate of nFET 108. At the time of operation, a current flows through the pFET 106 to the output 122. When an input 120 is at low level, namely, at a CMOS logic level '0', the nFET 108 is disconnected, the current flows out of the output 122, an output voltage is increased and this value is the voltage of shifted ECL logic '1'. Besides, when the input 120 is at high level, the nFET 108 is turned on and pulls the current from the output 122, and output power is lowered. This is the voltage value of shifted ECL logic '0'.
Inventors:
Robert Bee Manley
Application Number:
JP27848094A
Publication Date:
September 15, 2004
Filing Date:
October 18, 1994
Export Citation:
Assignee:
AGILENT TECHNOLOGIES, INC.
International Classes:
H03K19/003; H03K19/0185; H01L27/02; (IPC1-7): H03K19/0185
Domestic Patent References:
| JP3270408A | ||||
| JP4026228A | ||||
| JP6112808A |
Foreign References:
| US4791322 | ||||
| US4808852 | ||||
| US4998028 | ||||
| US5043605 |
Attorney, Agent or Firm:
Kimihisa Kato
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