Title:
LOGARITHMIC TRANSFORMATION CIRCUIT
Document Type and Number:
Japanese Patent JP3507530
Kind Code:
B2
Abstract:
PURPOSE: To provide a logarithmic transformation circuit operated over a wide voltage amplitude range of an input signal under a low power supply voltage.
CONSTITUTION: One-side terminals of resistors 5, 6, are connected to input terminals 1, 2 receiving an input signal via buffers 3, 4 respectively. PN junction elements 7, 8 are at least connected in series between the other terminal of the resistor 5 and the other terminal of the resistor 6 in an opposite polarity to each other. A bias circuit 9 is connected between a power supply Vcc and a connecting point of the PN junction elements 7, 8 and current sources 10-18 are connected to regulate a voltage drop of the resistors 5, 6 between both the terminals of the resistors 5, 6, across the resistor 6, and the power supply Vcc and a ground terminal GND and a voltage produced in the PN junction elements 5, 6 is extracted as an output signal subject to logarithmic transformation to output terminals 18, 19.
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Inventors:
Takashi Ueno
Mikio Koyama
Hiroshi Tanimoto
Mikio Koyama
Hiroshi Tanimoto
Application Number:
JP22996093A
Publication Date:
March 15, 2004
Filing Date:
September 16, 1993
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06G7/24; H03G7/08; (IPC1-7): G06G7/24
Domestic Patent References:
| JP5197820A |
Attorney, Agent or Firm:
Takehiko Suzue
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