PURPOSE: To obtain an FET, in which gate dielectric resistance is not lowered, series resistance among a source, a gate and a drain is small, space charge limitted currents in N+-I-N+ structure do not flow and saturation characteristics are improved, by isolating a gate electrode and N+ layers by an insulating film, reducing spaces among the N+ layers of source-drain layers and a gate metal and preventing contacts among the N+ layers and a semi-insulating substrate.

CONSTITUTION: Si+ ions are implanted into a Cr added semi-insulating GaAs substrate 11 at density of 2×1012pcs/cm3 at 50keV acceleration voltage to form an N type GaAs layer 12. Mo is sputtered and evaporated on the whole surface, and unnecessary Mo is dry-etched while using a photo-resist pattern as a mask to shape gate electrode 13. SiO2 31 is attached onto the whole surface in 3,000, and SiO2 is etched from the vertical direction in a wafer through parallel electrode type anisotropic dry etching to leave a side wall 21 in 3,000 thickness only on the side surface of the gate 13. An N+ GaAs layer is grown on the whole surface by utilizing the thermal decomposition of AsH3 and (CH3)Ga through an MOCVD method through which a crystal can be grown at a comparatively low temperature. A source electrode 14 and a drain electrode 15 are formed in a predetermined region in the surface of the N+ GaAs layer, thus obtaining a GaAs MESFET.