Title:
試験工程を簡略化できるメモリカード及びメモリカードの試験方法
Document Type and Number:
Japanese Patent JP4086584
Kind Code:
B2
Abstract:
In a memory card which includes a memory chip and a controller connected to the memory chip for the control of transferring a data from outside, the controller is provided with a buffer in which data is temporarily stored. In a first operation mode, the controller clears the data stored in the buffer after the data in the buffer is transferred to the memory chip. In a second operation mode, the controller does not clear the data stored in the buffer even after the data in the buffer is transferred to the memory chip. By the use of these modes, it becomes possible to write the data obtained by means of external transfer into the memory chip repeatedly for a plurality of times by means of internal transfer. Thus, it becomes unnecessary to repeat external transfer and internal transfer every time.
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Inventors:
Furukawa Hideyuki
Application Number:
JP2002231453A
Publication Date:
May 14, 2008
Filing Date:
August 08, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F3/06; G06F12/16; G06F3/08; G06K17/00; G06K19/07; G11C29/48
Domestic Patent References:
| JP2144644A | ||||
| JP10105659A | ||||
| JP6119508A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku