Title:
MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH01130385
Kind Code:
A
Abstract:
PURPOSE:To reduce the peak of a current flowing at the time of collective write by dividing a memory cell array into plural memory cell groups and collectively writing data in respective memory cell groups at different timings. CONSTITUTION:When one decoder DE receives the inverse of control signals Sc0-Sc15, '0' is collectively written in all memory cells MC in a memory cell group M corresponding to this decoder DE. Generation timings of control signals Sc, Sc1, Sc2... given to decoders DE0, DE1, DE2...DE15 for collective write are shifted from one another by actions of delay circuits DL1, DL2...DL15, and flash clear is performed in the order of memory cell groups M0, M1, M2...M15 while shifting the timing. Thus, the peak value of the current flowing at the time of flash clear is reduced.
Inventors:
ARAKI SHIGEO
TANIGUCHI HITOSHI
SUZUKI HIROYUKI
KOMATSU TAKASATO
TANIGUCHI HITOSHI
SUZUKI HIROYUKI
KOMATSU TAKASATO
Application Number:
JP29040887A
Publication Date:
May 23, 1989
Filing Date:
November 17, 1987
Export Citation:
Assignee:
SONY CORP
International Classes:
G11C11/41; G11C7/20; G11C11/419; (IPC1-7): G11C11/34
Domestic Patent References:
| JPS5914195A | 1984-01-25 |
Attorney, Agent or Firm:
Hideaki Ogawa