Title:
読み取り時間を短縮することができるメモリシステム
Document Type and Number:
Japanese Patent JP7146114
Kind Code:
B2
Abstract:
A bias circuit, a memory system, and a method of boosting a voltage level of a first bit line are provided. The bias circuit includes a first current generator, a second current generator, and a bit line bias generator. The first current generator is configured to generate a first replica charging current according to a charging current flowing through a voltage bias transistor. The second current generator is configured to generate a first replica cell current according to a cell current flowing through a common source transistor. The bit line bias generator is coupled to a first page buffer, the first current generator, and the second current generator, and configured to generate a bit line bias voltage, supplied to the first page buffer, according to a comparison of the first replica charging current and the first replica cell current.
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Inventors:
Weilong Chen
Jang Tan
Jang Tan
Application Number:
JP2021557114A
Publication Date:
October 03, 2022
Filing Date:
April 30, 2019
Export Citation:
Assignee:
Yangtze Memory Technologies Co.,Ltd.
International Classes:
G11C16/24; G11C7/12
Domestic Patent References:
| JP2015536520A | ||||
| JP2016170845A | ||||
| JP200679803A |
Attorney, Agent or Firm:
Murayama Yasuhiko
Shinya Mihiro
Tatsuhiko Abe
Shinya Mihiro
Tatsuhiko Abe