To obtain a circuit which is useful in managing a queue having a significant bit by including inputs for receiving a significant signal, inputs for receiving a shift signal, and an output for supplying a select signal responding to those signals to multiplexers coupled with the queue.
The 1st inputs for receiving the significant signal responding to a 1st group of significant bits, the 2nd inputs for receiving the shift signal responding to a 2nd group of significant bits, and the outputs for supplying the select signal responding to the shift signal and significant signal to the multiplexers MUXa to MUXc coupled with the queue. Respective queue items (a) to (c) have relative significant bits va to vc. Then the operation of a selected line and, therefore, control over data written in the queue is performed by a queue control circuit 300 according to the states of the significant bits va to vc.
MICHAEL KEVIN SHIROORA
FUN KUI REE
JOHN STEVEN MUEHCH
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