METHOD FOR FORMING THIN FILM OF CRYSTALLINE MATERIAL SILICON NITRIDE COVERING IN SHALLOW TRENCH ISOLATION STRUCTURE AND SHALLOW TRENCH ISOLATION STRUCTURE FOR INTEGRATED CIRCUIT DEVICE OF SUB MICRON, AND CRYSTALLINE MATERIAL SILICON NITRIDE COVERING

Japanese Patent JPH10214889

A

To contain a trapping center with a lower density than before conversion, by depositing an Si3N4 covering with a specific thickness in an STI structure by the low-pressure chemical vapor deposition method, performing speedy heat annealing under specific conditions immediately after depositing the covering, and converting Si3N4 from amorphous to a crystal material.

After a shallow trench is etched, a thin thermal oxide with a thickness of approximately 10nm is grown to eliminate an etching damage. Then, an Si3N4 covering with a thickness of 5-10nm is deposited on the upper surface of an oxide layer in amorphous state at a temperature of 720-780°C in a shallow trench isolation structure(STI). Then, immediately after the covering is deposited, a high-speed heat annealing is executed nearly for 60 seconds at 1,050-1,150°C in pure nitrogen or ammonium and the Si3N4 covering is converted from the amorphous state to the crystal material state of a low- temperature-hexagonal (d) Si3N4 phase.

JPH0770587	PROBLEM TO BE SOLVED: To manufacture a semiconductor integrated circuit structure.
JPH06342893	MANUFACTURE OF SEMICONDUCTOR DEVICE
JPH09213785	SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

HO HERBERT
HAMMERL ERWIN
DOBUZINSKY DAVID M
PALM J HERBERT
FUGARDI STEPHEN
AJMERA ATUL
MOSEMAN JAMES F
RAMAC SAMUEL C

JP2253198A

August 11, 1998

January 21, 1998

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SIEMENS AG (DE)
IBM (US)

H01L21/76; H01L21/318; (IPC1-7): H01L21/76; H01L21/318

Toshio Yano (1 outside)

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