Title:
METHOD AND SYSTEM OF EVALUATING CONDUCTOR IN SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3392597
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To determine a lifetime original to a metallic wiring easily and accurately by excepting the dispersion and irregularities of the lifetime of a conductor resulting from the unevenness of the shapes of the metallic wiring, an electrode, etc., constituting the conductor to be evaluated from evaluation elements.
SOLUTION: A conductor to be evaluated is formed onto a semiconductor substrate so that initial resistance is kept within a specified range (ST1). The conductor to be evaluated is supplied with a current under constant acceleration conditions, in which the current is brought to the same temperature and the same value, and the reliability of the conductor to be evaluated is tested (ST2). Data regarding the lifetime of the conductor to be evaluated are obtained (ST3). Consequently, parameters displaying reliability-lifetime characteristics are acquired by using a resistance value obtained and the data regarding the lifetime (ST4). Lastly, a future cumulative fraction defective is predicted by employing these parameters (ST5).
Inventors:
Matsuo Mie
Naoko Kaneko
Naoko Kaneko
Application Number:
JP21182295A
Publication Date:
March 31, 2003
Filing Date:
August 21, 1995
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/3205; H01L21/321; H01L21/60; H01L21/66; H01L23/52; G01R31/26; (IPC1-7): H01L21/66; G01R31/26; H01L21/3205; H01L21/60
Domestic Patent References:
| JP6209034A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)