To easily observe a signal, which is transmitted between internal circuits, from outside.

To a CPU 11, a storage circuit 15, a peripheral function block 16, and a general port 17 are connected by three internal buses which are a control bus 12, an address bus 13, and a data bus 14. Respective elements which are connected to the CPU 11 through the internal bus are mapped in an address space which is all accessible from CPUs 11. A general port 17 has a data register. Then while a control register 18 is so set as to output an internal signal to the outside, signals outputted onto the control bus 12, address bus 13, and data bus 14 are stored in a data register. The control register 18 is connected to the CPU 11 and its contents are rewritten under the control of the CPU 11. The value of the data stored in the control register 18 becomes the external output command of the internal signal.