Title:
MODULATOR
Document Type and Number:
Japanese Patent JP3260873
Kind Code:
B2
Abstract:
PURPOSE: To make a fast arithmetic operation possible and to save power consumption by simplifying a circuit by eliminating a multiplier used in a FIR filter.
CONSTITUTION: This modulator is equipped with memory circuits 17a-17c which classify the impulse response coefficient of the FIR filter into groups at every specific data and add data in which the specific data is multiplied by the impulse response coefficient in the group and store obtained data at every group, a means 13 which generates an address based on an input signal, and a means 14 which adds the output signals of the memory circuits 17a-17c outputted by the address. In other words, it is possible to provide the modulation circuit of 1/4πQPS without providing the FIR filter by utilizing the fact that the input data of the FIR filter can be specified, generating the address from the kind of the input data, setting the data in which they are added as the data for the memory circuits 17a-17c, and adding them.
Inventors:
Kazunari Sawada
Tamotsu Nagashima
Tamotsu Nagashima
Application Number:
JP34922492A
Publication Date:
February 25, 2002
Filing Date:
December 28, 1992
Export Citation:
Assignee:
Asahi Kasei Microsystem Co., Ltd.
International Classes:
G06G7/16; H03C3/00; H03H17/00; H03H17/06; H04J3/00; H04L27/20; (IPC1-7): H04L27/20
Domestic Patent References:
| JP59132267A | ||||
| JP4323932A | ||||
| JP3235553A | ||||
| JP4239245A | ||||
| JP6205056A | ||||
| JP6205057A | ||||
| JP6205059A |
Attorney, Agent or Firm:
Kazuo Watanabe
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