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Patent Searching and Data


Title:
MULTI-NODE COMPUTER SYSTEM AND METHOD FOR SPECIFYING FAULT OCCURRENCE CAUSE PLACE
Document Type and Number:
Japanese Patent JP2000242520
Kind Code:
A
Abstract:

To provide available device resources as much as possible by narrowing down a fault place and separating minimum faulty devices.

When a fault detection circuit 4A0 monitors a signal from a crossbar switch 5 and detects a fault between networks, it notifies the a fault information collection circuit 490 of the fault. The circuit 490 collects the transfer source node number of fault data and notifies a test execution circuit 480 of fault occurrence and the transfer source node number. The circuit 480 transmits a test execution request to an interruption control circuit 450, and the circuit 450 transmits an interruption signal to a CPU 20. Then, the CPU 20 instructs an operation decoding circuit 440 to transfer a test pattern from the transfer source node to a different transfer destination. The instruction is transferred to the switch 5 through a command transmission circuit 470 and an SW write circuit 420.


Inventors:
KOMATSU GOICHI
Application Number:
JP4220699A
Publication Date:
September 08, 2000
Filing Date:
February 19, 1999
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
G06F15/177; G06F11/22; G06F15/173; (IPC1-7): G06F11/22; G06F15/177
Attorney, Agent or Firm:
Katsuharu Sato