Title:
MULTIINPUT AND MULTIOUTPUT CONTENTION TYPE AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JP3388088
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve sensitivity in a multiinput and multioutput contention type amplifier circuit realized as a circuit for detecting a maximum value or a minimum value among the input signals of plural channels or the like.
SOLUTION: The maximum input detection circuit 1 detects the channel of larget input among the input signals Vin(1)-Vin(N) of the plural N channels. In this case, input terminals A1-AN are floated by coupling capacities C1-CN and feedback circuits F1-Fn for feeding back a low frequency component corresponding to the difference of output signals Vout(1)-Vout(N) and a predetermined output reference level Vref to the input terminals A1-AN are respectively provided for the respective channels. Thus, compensation is performed by a potential difference among the terminals of the coupling capacities C1-CN for the input offset of an analog amplifier circuit 2 and a DC component included in the respective input signals Vin(1)-Vin(N). In such a manner, a fine difference among the input signals of the respective channels is detected with high sensitivity.
Inventors:
Kunihiko Iizuka
Application Number:
JP10046196A
Publication Date:
March 17, 2003
Filing Date:
April 22, 1996
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G06G7/12; H03F3/72; H03K17/00; (IPC1-7): G06G7/12; H03F3/72
Domestic Patent References:
| JP5234770A | ||||
| JP2221870A | ||||
| JP8321747A |
Attorney, Agent or Firm:
Kenzo Hara
Previous Patent: BODY DETECTOR
Next Patent: NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT MANUFACTURING METHOD
Next Patent: NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT MANUFACTURING METHOD