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Title:
NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3388089
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To reduce the cell size of a nonvolatile semiconductor memory element having upper electrodes also serving as drive line, by using a ferroelectric film for the capacitance insulation film and patterning the upper electrodes and this insulation film at once.
SOLUTION: After forming transistors, an interlayer insulation film having an uppermost titanium oxide film 8 is formed. Contact holes are formed through this insulation film and filled with contact plugs, and then a titanium oxide film 12 and Pt film 13 are deposited on the entire surface. Using an etching gas contg. Cl2 and C2F6, the Pt film 13 is patterned into a specified shape. Using an etching gas contg. Cl2, and C2F6 or contg. SF6 and O2, the film 16 is patterned into a specified shape to form lower electrodes of capacitors.


Inventors:
Shigeo Ohnishi
Takao Kinoshita
Atsushi Kudo
Application Number:
JP10542196A
Publication Date:
March 17, 2003
Filing Date:
April 25, 1996
Export Citation:
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Assignee:
Sharp Corporation
International Classes:
H01L21/8247; C23F4/00; H01L21/02; H01L21/3213; H01L21/822; H01L21/8242; H01L21/8246; H01L27/04; H01L27/10; H01L27/105; H01L27/108; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/105; H01L21/822; H01L27/04
Domestic Patent References:
JP4356958A
JP897382A
JP7142698A
JP823073A
JP5299601A
JP52139372A
JP6163468A
JP3239323A
JP7147284A
Attorney, Agent or Firm:
Shintaro Nogawa (1 person outside)