Title:
MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JP3511320
Kind Code:
B2
Abstract:
PURPOSE: To output the mutually multiplied result of digital data as analog data by setting the weight of capacity coupling to an analog input voltage based on the digital data.
CONSTITUTION: This multiplication circuit is provided with plural first opening/ closing means SW11-SW14, and a first capacity coupler CP 1 is connected to each output. The capacity coupler CP1 is constituted by parallelly connecting capacitances C11-C15, one terminal of each of capacitances C11-C14 is connected to each of opening/closing means SW11-SW14, and one terminal of the capacitance C15 is grounded. Further, the output of the capacity coupler CP1 is inputted to an inverted amplifier INV1 composed of three stages of MOS inverters I1-I3, and the output of the inverted amplifier INV1 is connected through a feedback capacitance Cf1 to its input. Thus, this multiplication circuit weighs the prescribed analog input voltage more than two stages with the capacity coupler CP1, and the weight of this capacity coupler CP1 is set by controlling the opening/closing means based on the digital data.
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Inventors:
Kotobuki, Kokuriyou
Motohashi, Kazunori
Takatori, Sunao
Yamamoto, Makoto
Motohashi, Kazunori
Takatori, Sunao
Yamamoto, Makoto
Application Number:
JP26112294A
Publication Date:
March 29, 2004
Filing Date:
September 30, 1994
Export Citation:
Assignee:
YOZAN:KK
SHARP CORP
SHARP CORP
International Classes:
G06G7/16; G06J1/00; (IPC1-7): G06G7/16
Attorney, Agent or Firm:
平木 祐輔 （外１名）
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