Title:
MULTIPLIER CIRCUIT
Document Type and Number:
Japanese Patent JP3388603
Kind Code:
B2
Abstract:
PURPOSE: To eliminate a need to adjust a load resistor by constituting circuits, which obtain double waves of a sine wave and a NOT sine wave and those of a cosine wave and a NOT cosine wave, of double balanced differential amplifying circuits and adjusting the gains by negative feedback resistors connected to differential pairs.
CONSTITUTION: Each of a circuit 10 to obtain double waves of the sine wave and the NOT nine wave and a circuit 11 to obtain those of the cosine wave and the NOT cosine wave consists of two double balanced differential amplifying circuits. The sine wave and the NOT sine wave are inputted to upper differential pairs connected in parallel of the circuit 10, and the cosine wave and the NON cosine wave are inputted to lower differential pairs, thereby obtaining double waves of the sine wave and the NOT sine wave from the output side. The cosine wave and the NOT sine wave are inputted to the upper differential pair of one of two differential amplifying circuits of the circuit 11, and the cosine wave and the sine wave are inputted to the lower differential pair, and the sine wave and the NOT cosine wave are inputted to the upper differential pair of the other differential amplifier circuit, and the NOT sine wave and the NOT cosine wave are inputted to the lover differential pair, thereby obtaining double waves of the cosine wave and the NOT cosine wave from the output side.
Inventors:
Kouichi Sakai
Application Number:
JP5516293A
Publication Date:
March 24, 2003
Filing Date:
February 19, 1993
Export Citation:
Assignee:
Toko Co., Ltd.
International Classes:
G06G7/16; G06G7/163; G06G7/22; (IPC1-7): G06G7/163; G06G7/22
Domestic Patent References:
| JP55913A | ||||
| JP61170872A | ||||
| JP5259768A | ||||
| JP58129810A | ||||
| JP6111037A |