Title:
MULTIPLIER CIRCUIT
Document Type and Number:
Japanese Patent JP3388604
Kind Code:
B2
Abstract:
PURPOSE: To eliminate a need to adjust a load resistor and to realize good series connection by constituting a circuit, which obtains double waves of a sine wave and a NOT sine wave, of a logarithmic convertor circuit and plural double balanced differential amplifier circuits.
CONSTITUTION: A circuit 10 to obtain double waves of the sine wave and the NOT sine wave consists of the logarithmic convertor circuit and two double balanced differential amplifier circuits, and the logarithmic convertor circuit essentially consists of transistors TRs Q25 and Q26 and diodes D1 and D2 forming the differential pair. A circuit 11 to obtain double waves of a cosine wave and the NOT cosine wave consists of two double balanced differential amplifier circuits. Inputs subjected to logarithmic conversion are applied to upper differential pairs of two double balanced differential amplifier circuits of the circuit 10. Since the non-linearity of the logarithmic convertor circuit and that of TRs forming differential pairs of double balanced differential amplifier circuits are opposite, the product of inputs of upper and lower differential pairs is obtained as the output of each double balanced differential amplifier circuit, and further, logarithmic conversion is released.
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Inventors:
Kouichi Sakai
Application Number:
JP5516393A
Publication Date:
March 24, 2003
Filing Date:
February 19, 1993
Export Citation:
Assignee:
Toko Co., Ltd.
International Classes:
G06G7/16; G06G7/163; G06G7/22; (IPC1-7): G06G7/163; G06G7/22
Domestic Patent References:
| JP55913A | ||||
| JP61170872A | ||||
| JP5259768A | ||||
| JP58129810A | ||||
| JP6111037A | ||||
| JP5348440A |