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Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JP2003141440
Kind Code:
A
Abstract:

To provide a multiplier capable of being operated with low voltage with a simple constitution.

The total sum of emitter currents of a pair of first transistors composed of a transistor Q13 and a transistor Q14, and a transistor Q11, and the total sum of emitter currents of a pair of second transistors composed of a transistor Q15 and a transistor Q16, and a transistor Q12 are controlled to be a constant current I0. The differential voltage v1 is inputted to pairs of bases respectively of the pairs of the first and second transistors, and the collector current at one side changed to opposite polarity with respect to the change of the differential voltage v1 are composed on a terminal T0 and a terminal T0'. The composed current flows to the resistor R11 and a resistor R12 as the differential current. A signal corresponding to a product of the differential voltage v2 and the differential voltage v1 inputted between the bases of the transistor Q11 and the transistor Q12 is outputted from a part between the terminal T0 and the terminal T0'.


Inventors:
MATSUGAKI YOSHIKATSU
MOROTA AKINOBU
Application Number:
JP2001342348A
Publication Date:
May 16, 2003
Filing Date:
November 07, 2001
Export Citation:
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Assignee:
TEXAS INSTRUMENTS JAPAN
International Classes:
G06G7/163; H03D7/14; H03F3/45; (IPC1-7): G06G7/163; H03D7/14; H03F3/45
Attorney, Agent or Firm:
Takahisa Sato



 
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