Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JP3385537
Kind Code:
B2
Abstract:
PURPOSE: To provide a multiplier which is capable of performing a low voltage operation by indepedently enabling the setting of a signal level to be multiplied.
CONSTITUTION: The signal input circuit D2 of a signal V2 is composed of transistors Q11 to Q14, an emitter resistance Re and a current source 110, the signal input circuit D1 of a signal V1 is composed of transistors Q15 to Q20, a collector load resistor Rc, and a current suction circuit is composed of transistors Q13 and Q14 and transistors Q19 and Q20, respectively. By the current suction circuit, the output current of the signal input circuit D2 is received and delivered in the signal input circuit D1 and the collector output of the signal input circuit D1 is taken out as multiplication output V0. Because the potential levels of the signals V1 and V2 can be independently determined, a low voltage operation becomes possible.
Inventors:
Yasuhide Tanaka
Application Number:
JP28769992A
Publication Date:
March 10, 2003
Filing Date:
October 26, 1992
Export Citation:
Assignee:
Japan Radio Co., Ltd.
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
| JP6120810A |
Attorney, Agent or Firm:
Yosuke Goto (1 person outside)
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