Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JP3533747
Kind Code:
B2
Abstract:
PURPOSE: To provide an analog multiplier capable of expanding input voltage range having high linearity while maintaining a low voltage operation.
CONSTITUTION: The multiplier is constituted of two multi-tail cells (cells capable of driving plural transistors(TRs) by a common current source) A, B. Each of the cells A, B is constituted of a TR pair to which a 1st signal (voltage Vx) is differentially inputted and one or more TRs (in the case of two TRs or more, their input terminals and output terminals are connected in common) to which one (in-phase voltage) or the other (reverse phase voltage) of the differential inputs of a 2nd signal (voltage Vy) is inputted. Output pairs having respectively different polarity in the TR pairs of respective cells A, B are connected in common as a differential output pair and the output terminals of TRs for inputting the 2nd signal are connected in common.
Inventors:
Kimura, Katsuharu
Application Number:
JP7835295A
Publication Date:
May 31, 2004
Filing Date:
March 09, 1995
Export Citation:
Assignee:
NEC CORP
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Attorney, Agent or Firm:
机 昌彦 （外２名）