PURPOSE: To achieve higher speed operation by minimizing an insulating substrate and shortening the length of wiring.

CONSTITUTION: Insulating substrates 1, 2 and 3 mounted with semiconductor chips 6 are stacked with one another. The stacked insulating substrates 1, 2 and 3 are electrically connected through their external leads 4. Alternatively, insulating substrates mounted with semiconductor chips on their both sides may be stacked. The two lower insulating substrates 1 and 2 are mounted with a cache memory; the uppermost insulating substrate 3 is mounted with a CPU, FPU and BIU. The insulating substrate 3 is also mounted with a heat sink 9.