Title:
不揮発性半導体記憶素子を用いたニューラルネットワーク演算回路
Document Type and Number:
Japanese Patent JP6858870
Kind Code:
B2
Abstract:
A neural network computation circuit that outputs output data (y) according to a result of a multiply-accumulate operation between input data (x0to xn) and connection weight coefficients (w0to wn), the neural network computation circuit includes computation units (PU0 to PUn) in each of which a non-volatile semiconductor memory element (RP) and a cell transistor (T0) are connected in series between data lines (BL0, SL0), a non-volatile semiconductor memory element (RN) and a cell transistor (T1) are connected in series between data lines (BL1, SL1), and gates of the transistors (T0, T1) are connected to word lines (WL0 to WLn). The connection weight coefficients (w0to wn) are stored into the non-volatile semiconductor memory elements (RP, RN). A word line selection circuit (30) places the word lines (WL0 to WLn) in a selection state or a non-selection state according to the input data (x0to xn). A determination circuit (50) determines current values flowing in data lines (BL0, BL1) to output output data (y).
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Inventors:
Kazuyuki Kono
Takashi Ono
Masayoshi Nakayama
Reiji Mochida
Yuriko Hayata
Takashi Ono
Masayoshi Nakayama
Reiji Mochida
Yuriko Hayata
Application Number:
JP2019540910A
Publication Date:
April 14, 2021
Filing Date:
August 29, 2018
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G06F12/00; G06G7/60; G06N3/063; G11C11/54
Domestic Patent References:
| JP2010146514A | ||||
| JP2003283003A |
Foreign References:
| US20140122402 |
Attorney, Agent or Firm:
Hiromori Arai
Eisaku Teratani
Shinichi Michisaka
Eisaku Teratani
Shinichi Michisaka