Title:
アナログ－デジタル変換に先立つ初期統合をもたらすニューラル・ネットワーク回路
Document Type and Number:
Japanese Patent JP7398552
Kind Code:
B2
Abstract:
Neural network circuits providing early integration before ADC are described. Comparators are adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a vector of bits indicating whether the plurality of analog voltages exceed the predetermined threshold, and transmit the vector of bits via a network. At least one ADC is configured to convert the plurality of analog voltages to a vector of digital values, and transmit the vector of digital values via the network. At least one modulator is configured to receive the vector of bits from the network, provide pulses to each of a plurality of input wires of a second synaptic array based on the vector of bits, receive the vector of digital values from the network, and provide pulses to each of the plurality of input wires based on the vector of digital values.
Inventors:
Barre, Jeffrey
Application Number:
JP2022512450A
Publication Date:
December 14, 2023
Filing Date:
July 17, 2020
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G06N3/063; G06G7/60; G11C11/54
Domestic Patent References:
| JP2018109968A | ||||
| JP2005122467A | ||||
| JP2018160007A |
Attorney, Agent or Firm:
Tadashi Taneichi