PURPOSE: To suppress the deterioration in a readout speed by providing additionally a 2nd P-channel transistor(TR) and a 2nd N-channel TR inserted in series between a power supply and ground whose connecting point connects to an output terminal so as to reduce a through-current of the output TR.

CONSTITUTION: An input DIN changes from an H level to an L level, a node B reaches an L level earlier than a node A via a NAND circuit NA1 and an inverter INV2. Before an output TR P1 is turned on, an output TR N1 is turned off. Simultaneously, an output node of a NOR circuit NR2 changes to an L level via an output node K of the circuit NA1 Simultaneously and an output TR N2 is turned off before the output TR P1 is turned on. Through the operation above, a through-current flowing to the output TR N2 is prevented and the deterioration in the readout speed is suppressed.