Title:
PARALLEL BIT TEST CIRCUIT SHARING OUTPUT DRIVER, PARALLEL BIT TEST METHOD UTILIZING THE SAME, AND ITS SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3661979
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a test circuit capable of enhancing an output rate of data during normal input and output and reducing a difference in the output rates of respective output data.
SOLUTION: A parallel bit test circuit comprises normal drivers(ND) 101-115, a comparison circuit 117, and test drivers (DRI) 119-125. In a memory cell array 160, 8 data are respectively amplified by corresponding sense amplifiers (not illustrated) to be data line outputs TD00/TD0B0 to TD07/TD0B7. The comparison circuit 117 outputs a signal obtained by comparing the data line outputs TD00-TD07 in response to a comparison bit number in a parallel bit test mode. Each of the test drivers 119, 121, 123, 125 receives the corresponding output signal from the comparison circuit 117 and transmits it to a global output line.
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Inventors:
Kin Chur
Application Number:
JP7452099A
Publication Date:
June 22, 2005
Filing Date:
March 18, 1999
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C29/00; G11C29/12; G01R31/28; G11C29/34; (IPC1-7): G11C29/00; G01R31/28
Domestic Patent References:
| JP63140499A | ||||
| JP3222199A | ||||
| JP2180000A | ||||
| JP6089596A | ||||
| JP5020899A | ||||
| JP5135600A | ||||
| JP9120698A | ||||
| JP1286200A |
Attorney, Agent or Firm:
Yasunori Otsuka
Kenichi Matsumoto
Kenichi Matsumoto