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Patent Searching and Data


Title:
PIN GRID ARRAY
Document Type and Number:
Japanese Patent JPS6320859
Kind Code:
A
Abstract:

PURPOSE: To conduct the mounting of a semiconductor chip and the work of wire bonding easily by using existing facilities by forming constitution in which a circuit body to which the semiconductor chip is mounted is insert-molded and buried into a substrate.

CONSTITUTION: A circuit body 3 to which a semiconductor chip 4 is mounted is insert-molded and buried into a substrate 1. A radiator 5 disposed to the circuit body 3 is insert-molded and buried into the substrate 1 under the state in which one part of the radiator 5 is exposed from the surface of the substrate 1. Through-holes 6 bored to the circuit body 3 are filled with a thermal and/or electric good conductive material 7, the semiconductor chip 4 and the radiator 5 are connected through the good conductive material 7, and a plurality of pins 2 insert-molded and fastened into the substrate 1 are projected from the substrate under the state in which base sections are connected to the circuit body 3. The semiconductor chip 4 is mounted previously before it is fitted into the substrate 1, thus conducting mounting and the work of wire bonding under the state in which there is no pin 2.


Inventors:
HIRATA ATSUMI
Application Number:
JP16497686A
Publication Date:
January 28, 1988
Filing Date:
July 14, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H01L23/34; H01L23/12; H01L23/28; H05K1/02; (IPC1-7): H01L23/12; H01L23/28; H01L23/34; H05K1/02
Attorney, Agent or Firm:
Ishida Choshichi