To provide a phase locked loop(PLL) circuit with high precision and high reliability.

A phase comparator 5 generates a lead phase error signal E1 depending on a phase difference between a front edge (object phase point) of a right window produced by a right window signal WR and a reference phase point of a frequency division reference clock signal S2 when a control object clock signal S3 is led from the frequency division reference clock signal S2, and the phase comparator 5 generates a lag phase error signal E1 depending on a phase difference between a tail edge (object phase point) of a left window produced by a left window signal WL and a reference phase point of the frequency division reference clock signal S2 when a control object clock signal S3 is lagged from the frequency division reference clock signal S2.