Title:
POLYNOMIAL DIVISION CIRCUIT AND EUCLIDEAN DECODING CIRCUIT
Document Type and Number:
Japanese Patent JP2020098994
Kind Code:
A
Abstract:
To provide a polynomial division circuit suitable for Euclidean decoding.SOLUTION: A division circuit 50 for obtaining a greatest common divisor polynomial of a syndrome polynomial and xwhere the number of continuous roots of the generator polynomial is denoted as 2t, includes: a shift register 30 having 2t first registers; a linear feedback shift register 10 having 2second registers to which XOR of values of a preceding stage and multiplication results of values of a highest stage and a first register of the preceding stage; a third register for outputting to the second register in a lowest stage; and a circuit for inputting 1 into the second register of the highest stage and 0 in the second and third registers of the other stages before a first division, inputting a value of the first register after the previous division into the second and third registers as a coefficient of the divisor polynomial before a second and subsequent divisions; inputting coefficients of the syndrome polynomial into the first register before the first division, and inputting the second and third registers after the previous division into the first register as coefficients of the divisor polynomial before the second and subsequent divisions.SELECTED DRAWING: Figure 6
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Inventors:
OKAMOTO MASAAKI
Application Number:
JP2018236224A
Publication Date:
June 25, 2020
Filing Date:
December 18, 2018
Export Citation:
Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H03M13/15; G06G7/20
Attorney, Agent or Firm:
Shuhei Katayama