Title:
ディープラーニングの人工ニューラルネットワーク内のアナログニューラルメモリ内に不良メモリセルを含む行又は列に関する冗長メモリアクセス
Document Type and Number:
Japanese Patent JP7394827
Kind Code:
B2
Abstract:
Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
Inventors:
Van Tran, Hugh
Hong, Stanley
Boo, Sun
Li, Ann
Pam, Hien
Nuen, Ka
Trang, Han
Hong, Stanley
Boo, Sun
Li, Ann
Pam, Hien
Nuen, Ka
Trang, Han
Application Number:
JP2021500584A
Publication Date:
December 08, 2023
Filing Date:
June 07, 2019
Export Citation:
Assignee:
SILICON STORAGE TECHNOLOGY, INC.
International Classes:
G06N3/063; G06G7/60; G11C11/54; G11C16/04; G11C29/00
Foreign References:
| US20180173600 | ||||
| US20170337466 | ||||
| US5729152 |
Attorney, Agent or Firm:
Patent Attorney Corporation Wisdom International Patent and Trademark Office