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Title:
ROW DECODER OF FLASH MEMORY AND ERASING METHOD OF FLASH MEMORY USING THE ROW DECODER
Document Type and Number:
Japanese Patent JP2004055134
Kind Code:
A
Abstract:

To provide a row decoder of a flash memory that can prevent a breakdown phenomenon in an ONO insulating film occurring in erasing operation in an E/W cycle test or the like, and to provide an erasing method of the flash memory using the row decoder.

The row decoder includes a PMOS transistor that receives a first input signal in a gate electrode and is connected between a first power supply terminal an a first node; a first NMOS transistor that receives the first input signal at the gate electrode and is connected between the first and second nodes; a second NMOS transistor that receives a second input signal at the gate electrode and is connected between the second node and an earth terminal; and a switch means that receives a third input signal in the gate electrode and is connected between the second node and a second power supply terminal. In this case, the first node is connected to the word line of a memory matrix.


Inventors:
KIM KI SEOG
LEE KEUN WOO
BOKU NARIMOTO
JEON YOO NAM
Application Number:
JP2003274800A
Publication Date:
February 19, 2004
Filing Date:
July 15, 2003
Export Citation:
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Assignee:
HYNIX SEMICONDUCTOR INC
International Classes:
G11C16/06; G11C16/02; G11C16/08; G11C16/14; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792; G11C16/16; G11C29/00; (IPC1-7): G11C16/06; G11C16/02; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Teruichi Hase
Maki Kamiya