SAMPLED AMPLITUDE READ CHANNEL AND DIGITAL DATA READ METHOD

Japanese Patent JPH1092119

A

To realize a discrete time filter of a high order and an analog filter of a lower order by using a sampling read channel which is provided with a sampling device, with an adaptive equalizer, with an interpolated timing recovery and with a discrete time sequence detector.

In a sampled amplitude read channel, an interpolated timing recovery B100 is provided instead of a conventional sampled timing recovery. In addition, a write frequency synthesizer 52 generates a baud rate clock 54 which is given to a write circuit 9. A sampling device 24, a discrete time equalizer filter B103 and the interpolated timing recovery B100 generate the asynchronous read clock 54 which is clock-matched at a frequency CDR 30 with reference to a present zone.

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BLISS WILLIAM G
BEHRENS RICHARD T
DU LI
REED DAVID
SPURBECK MARK

JP10641097A

April 10, 1998

April 23, 1997

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CIRRUS LOGIC INC

G11B5/09; G11B20/10; G11B20/14; G11B20/18; H03H15/00; H03H17/00; H03H17/06; H04L25/03; G11B20/12; (IPC1-7): G11B20/14; G11B5/09; G11B20/18; H03H15/00; H03H17/00; H03H17/06; H04L25/03

Shusaku Yamamoto

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