To constitute an intermediate-withstand voltage MOS transistor etc., in a dual-gate.

A p-type well 2 and an n-type well 3 are adjacently formed on a silicon substrate 1 by respectively using a p-type well mask 2 and an n-type well mask 3. Then a polysilicon layer 5 is deposited on the whole surface of a gate insulating film 4 by an LPCVD method. In addition, a first photoresist layer 6 is formed by using the p-type well mask, and the polysilicon layer 5 is set to an n-type by implanting the ion of an n-type impurity, such as the arsenic etc., into the layer 5 by using the photoresist layer 6 as an ion implanting mask. Thereafter, the first photoresist layer 6 is removed, a second photoresist layer 7 having an opening on the n-type well 3 is formed by using the n-type well mask, and the polysilicon layer 5 is set to a p-type by implanting the ion of a p-type impurity, such as the boron etc., into the layer 5 by using the second photoresist layer 7 as an ion implanting mask.