Title:
半導体装置とその製造方法
Document Type and Number:
Japanese Patent JP7117260
Kind Code:
B2
Abstract:
To improve performance of a semiconductor device.SOLUTION: A semiconductor device comprises a power MOSFET 1 and a snubber capacitor connected between a drain and a source of the power MOSFET. The snubber capacitor includes a capacitor electrode CE1 connected to the drain and a capacitor electrode CE2 connected to the source. The capacitor electrode CE1 extends in a Y direction and is connected, in its end, to a coupling wire WLC1 extending in an X direction. Further, a pad electrode SNP1 to which a probe needle is abutted in a screening step of the snubber capacitor is connected to the coupling wire WLC1. The pad electrode SNP1 is connected to the drain by a snubber wire ESN1 which is disposed on the pad electrode SNP1.SELECTED DRAWING: Figure 4
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Inventors:
Moriya Taro
Hironori Kudo
Satoshi Satoshi
Hironori Kudo
Satoshi Satoshi
Application Number:
JP2019049666A
Publication Date:
August 12, 2022
Filing Date:
March 18, 2019
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/336; H01L21/3205; H01L21/768; H01L23/522; H01L29/78
Domestic Patent References:
| JP2017163107A | ||||
| JP20194042A | ||||
| JP201881949A | ||||
| JP2015207736A | ||||
| JP2018157192A | ||||
| JP2014523649A | ||||
| JP1064938A |
Foreign References:
| WO2007116501A1 |
Attorney, Agent or Firm:
Patent Attorney Tsutsui International Patent Office