Title:
半導体装置とその製造方法
Document Type and Number:
Japanese Patent JP7226580
Kind Code:
B2
Abstract:
A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.
More Like This:
| WO/2011/142066 | CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT |
| JP2005236233 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD |
| JP2007149768 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE |
Inventors:
Hirofumi Kida
Tomita Eiki
Tomohiko Mori
Hideya Yamadera
Tomita Eiki
Tomohiko Mori
Hideya Yamadera
Application Number:
JP2021553239A
Publication Date:
February 21, 2023
Filing Date:
October 24, 2019
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H01L29/78; H01L21/336; H01L29/12
Domestic Patent References:
| JP2019071338A | ||||
| JP2018182197A | ||||
| JP2019165165A |
Foreign References:
| WO2016104264A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation Kaiyu International Patent Office