Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2001093861
Kind Code:
A
Abstract:
To solve the problem of making causing increased gate resistance high by the fact that the tapered configuration of a groove for embedding a gate electrode makes it hard to implement complete embedding, hence producing voids in the groove and decreasing the cross section of the gate electrode.
A groove is formed in a first interlayer insulating film 6 deposited on a semiconductor substrate 1, such that by making the groove have an inverted tapered configuration, a gate electrode 8 can be embedded in the groove so as not to produce voids in the subsequent step.
Inventors:
MATSUDA SATOSHI
Application Number:
JP26834599A
Publication Date:
April 06, 2001
Filing Date:
September 22, 1999
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L29/78; H01L21/285; H01L21/336; (IPC1-7): H01L21/285; H01L21/336; H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)