Title:
SEMICONDUCTOR DEVICE AND PRODUCT-SUM COMPUTATION DEVICE
Document Type and Number:
Japanese Patent JP2019179499
Kind Code:
A
Abstract:
To provide a semiconductor device and a product-sum computation device which further reduce a mounting area per synapse, and thereby enable integration with higher density.SOLUTION: A semiconductor device comprises: a plurality of synapses in which a non-volatile variable resistor element taking a first resistance value and a second resistance value lower than the first resistance value and a fixed resistor element having higher resistance value than the second resistance value are connected in series; and an output line outputting the total sum of electric currents flowing through the plurality of synapses.SELECTED DRAWING: Figure 3
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Inventors:
KOBAYASHI TOSHIYUKI
MORIMOTO RUI
OKUNO JUN
TSUKAMOTO MASANORI
SHUDO YUSUKE
MORIMOTO RUI
OKUNO JUN
TSUKAMOTO MASANORI
SHUDO YUSUKE
Application Number:
JP2018069791A
Publication Date:
October 17, 2019
Filing Date:
March 30, 2018
Export Citation:
Assignee:
SONY CORP
SONY SEMICONDUCTOR SOLUTIONS CORP
SONY SEMICONDUCTOR SOLUTIONS CORP
International Classes:
G06G7/60; G06N3/063; H01L45/00; H01L49/00
Attorney, Agent or Firm:
Miaki Kametani
Tetsuo Kanamoto
Koji Hagiwara
Kazuki Matsumoto
Tetsuo Kanamoto
Koji Hagiwara
Kazuki Matsumoto