PURPOSE: To optimize layout of a clock system circuit by providing a bonding pad where a single phase basic clock signal is input and a clock dividing circuit provided closed to the bonding pad for forming a plurality of phases of internal clock signals based on the basic clock signal.

CONSTITUTION: A single phase of base clock signal CP having frequency four times an internal clock signal is supplied from a clock generation circuit provided outside via a bonding pad CP. The basic clock signal CP is frequency divided into four phase internal clock signals 1 to 4 by a clock frequency dividing circuit CD placed close to the bonding pad CP, and then distributed and supplied to a logic circuit LC via a clock amplifier CA placed in the proximity of the center of a semiconductor substrate surface. As a result, clock input signal of a logic integrated circuit device is unified and the length of signal line between respective units in the clock amplifier CA and the logic circuit LC is averaged so that interphase skew of a plurality of phases of internal clock signals can be suppressed, thereby stabilizing operation of logic integrated circuit device.