PURPOSE: To unnecessitate fusing by irradiation with a laser beam, to improve a production yield and to reduce testing costs by using a ferroelectric memory cell for a storage element of a defective address.

CONSTITUTION: A defective address storage circuit 20 is provided with a ferroelectric memory cell array, a latch type sense-amplifier, a pre-charging/ writing circuit, etc. When a power source is switched on, the power-on signal 'PWRON' transites from 'L' to 'H', and controls a bit line potential, a self- board bias and an access control circuit, etc. Further, all the bit lines are individually set to a potential Vss by making the pre-charging circuit 13 on when the power source for the defective address recording circuit 20 is switched on by PWRON, and a fear of inverse polarization of the ferroelectric is eliminated. And a word line driving circuit 10 for the defective address storage circuit generates a word line signal FWL for a specified period and pre-charges the bit line pair before driving each transistor on the memory cell to be ON-state.