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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2008235625
Kind Code:
A
Abstract:

To provide a semiconductor integrated circuit which contains a backflow preventing circuit for blocking a through current when a DC power supply is connected to power terminals at reverse polarity, and which can improve the noise characteristic of an internal circuit in its reference potential.

The semiconductor integrated circuit comprises a P type semiconductor substrate, first and second power terminals to which the DC power supply is applied, an internal circuit having first potential supplied from the first power terminal and second potential supplied from a reference node connected to the semiconductor substrate, a resistor connected at its one end to the first power terminal, and an N-channel transistor including a source/drain region formed in a P type region formed in an N well of the semiconductor substrate to be connected between the first power terminal and the reference node and also including a gate connected to the other end of the resistor. The transistor is turned on when the DC power supply is normally connected and turned off when the DC power supply is connected at reverse polarity.


Inventors:
KUWANO SHUNICHI
Application Number:
JP2007073994A
Publication Date:
October 02, 2008
Filing Date:
March 22, 2007
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L21/8238; H01L21/822; H01L27/04; H01L27/08; H01L27/092
Domestic Patent References:
JPH11113169A1999-04-23
JPH08308116A1996-11-22
JP2003339117A2003-11-28
JP2002232279A2002-08-16
Attorney, Agent or Firm:
Masaaki Utsunomiya
Mutsumi Yanase
Harada victory
Atsushi Watanabe