Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4158214
Kind Code:
B2
Abstract:
A semiconductor integrated circuit having bias circuits each including different reference resistor is disclosed. The semiconductor integrated circuit comprises a reference voltage generating circuit which outputs a reference voltage, a first bias circuit connected to the reference voltage generating circuit. The first bias circuit has a first reference load element formed of a first material and generates a first bias voltage. The semiconductor integrated circuit further comprises a first driver circuit connected to the first bias circuit. The first driver circuit drives a first load element formed of the first material based on the first bias voltage. The semiconductor integrated circuit further comprises a second bias circuit connected to the reference voltage generating circuit and a second driver circuit connected to the second bias circuit. The second bias circuit has a second reference load element formed of a second material. The second driver circuit drives a second load element formed of the second material based on the second bias voltage.
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Inventors:
Hisao Otake
Application Number:
JP29980197A
Publication Date:
October 01, 2008
Filing Date:
October 31, 1997
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L21/822; H01L27/04; G05F3/20; G06G7/12; H03F1/30; H03F3/45
Domestic Patent References:
| JP9219629A | ||||
| JP4323707A | ||||
| JP4128909A | ||||
| JP2137259A | ||||
| JP64010709A | ||||
| JP63145345U |
Attorney, Agent or Firm:
Minoru Maeda