To provide a semiconductor memory device setting a negative threshold voltage to memory cells and performing a stable operation.

The semiconductor memory device includes: a memory cell array wherein a plurality of memory cells connected to word lines and bit lines are arranged in matrix and a negative threshold voltage can be set to the memory cells; and a control circuit for controlling potentials of the word lines and bit lines. In the control circuit, when a reading operation of the negative threshold voltage is performed from the memory cells connected to a first bit line BLo among the bit lines, a positive first voltage Vfix is supplied to a second bit line BLe arranged adjacent to the first bit line, a well wherein the memory cell array is formed, and a source line SRC of the memory cell array, and a positive voltage lower than the first voltage is supplied to the word line of a selected cell.