PURPOSE: To reduce the area of one transistor type memory cell consisting of a MIS capacitance element and a switching MISFET, and to improve the degree of integration by extending a word line in the same direction as the channel width of the MISFET formed under a gate electrode constituting the memory cell and unifying the gate electrode and the word line.

CONSTITUTION: A thick field insulating film 2 is formed to the peripheral section of an n- type semiconductor substrate 1, the surface of the substrate 1 surrounded by the insulating film 2 is coated with a thin gate oxide film 2', and an opening is bored made correspond to a source region in a switching MISFET connected to a bit line. Polycrystalline Si films 3 containing a p type impurity are deposited in the opening directly and on other regions through the film 2', a p+ type source region 4 is formed in the opening through heat treatment, and a gate electrode 3' for an MIS capacitance element is shaped on the source region 4. The films 3' composed of the polycrystalline Si films 3 on the film 2' are surrounded by an SiO2 film 3", and gate electrodes 5 for the MISFET overlapped between the film 3" and the electrode 3' are formed.