PURPOSE: To simultaneously execute multiplication and addition at high speed by constituting a unit by means of two input registers, a multiplier, two intermediate registers, an adder and an output register.

CONSTITUTION: When a multiplier and a multiplicand are respectively inputted to two input registers RA and RB in synchronizing with a first clock CK1 and they are held, the multiplier MUL executes an operation till two intermediate results before the addition of a final stage in an arbitrary multiplication algorithm is executed for the values of the input registers RA and RB, and respectively inputs them to the two intermediate registers PH and PL in synchronizing with second clock CK2 so as to hold them. The adder ADDER inputs three values of the intermediate registers PH and PL and the register RD so as to add them. Then, it inputs and holds an addition result to the output register RD in synchronizing with a third clock CK3. Thus, multiplication and addition can simultaneously be executed at high speed within one cycle.