Title:
薄膜キャパシタ及びこれを内蔵する回路基板、並びに、薄膜キャパシタの製造方法
Document Type and Number:
Japanese Patent JP7428000
Kind Code:
B2
Abstract:
Disclosed herein a thin film capacitor that includes a lower electrode layer, an upper electrode layer, and a dielectric layer disposed between the lower electrode layer and the upper electrode layer. The dielectric layer has a through hole. The upper electrode layer has a connection part connected to the lower electrode layer through the through hole and an electrode part insulated from the connection part by a slit. A surface of the lower electrode layer that contacts the connection part through the through hole includes an annular area positioned along an inner wall surface of the through hole and a center area surrounded by the annular area. The annular area is lower in surface roughness than the center area.
More Like This:
| JPH08222474 | MANUFACTURE OF CERAMIC ELECTRONIC COMPONENT |
| JP2022094282 | MULTILAYER ELECTRONIC COMPONENT |
| JP2023099412 | LAMINATE-TYPE ELECTRONIC COMPONENT |
Inventors:
Yuki Yukawa
Tatsuo Namikawa
Akira Iioka
Atsuo Matsutani
Hitoshi Saita
Kazuhiro Yoshikawa
Tatsuo Namikawa
Akira Iioka
Atsuo Matsutani
Hitoshi Saita
Kazuhiro Yoshikawa
Application Number:
JP2020026806A
Publication Date:
February 06, 2024
Filing Date:
February 20, 2020
Export Citation:
Assignee:
SAE Magnetics(H.K.)Ltd.
International Classes:
H01G4/30; H01G4/33; H05K3/46
Domestic Patent References:
| JP2015095587A | ||||
| JP2013065687A | ||||
| JP2012054520A |
Attorney, Agent or Firm:
Mitsuhiro Washito
Ogata Japanese
Ogata Japanese
Previous Patent: Tile structures and tile units
Next Patent: Toner for developing electrostatic images and method for producing the same
Next Patent: Toner for developing electrostatic images and method for producing the same