Title:
THRESHOLD LEVEL ELEMENT
Document Type and Number:
Japanese Patent JP3444792
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To allow the element to conduct an logical arithmetic operation regardless of a fewer number of transistors(TRs) through the configuration of the element such that an input signal controls excitation of each transistor(TR) and a comparison inverter compares an output voltage signal appearing based on a sum of drain currents of each TR with a threshold level and provides an output of comparison result.
SOLUTION: An amplification factor β is set to MIS TRs 21, 22,...m corresponding to respective ωi so as to set a threshold level of a comparison inverter 30 at a value corresponding to '1' in a term sin(ΣωiXi-1) of a logical equation Y=sin(Σω-iXi-1), where ω=Wi/T (Wi is a weight of an i-th input and T is a threshold level). One terminal of each of the MIS TRs 21, 22,...m is pulled up to a power supply and the other terminal of each of them connects to ground via a TR 20. Then drain currents of the MIS TRs 21, 22,...m are summed and a voltage depending on the cross-reference between the sum current and an output of the TR 20 is given to the comparison inverter 30 which compares the voltage with a threshold level.
Inventors:
Victor I Bershawski
Application Number:
JP22839898A
Publication Date:
September 08, 2003
Filing Date:
August 12, 1998
Export Citation:
Assignee:
Monolith Co., Ltd.
International Classes:
H03K19/20; G06G7/60; H03K19/00; H03K19/23; (IPC1-7): H03K19/20; G06G7/60; H03K19/00
Domestic Patent References:
| JP36679A |
Other References:
【文献】国際公開96/021277(WO,A1)
Attorney, Agent or Firm:
Masaharu Seki