THRESHOLD VALUE LOGIC CIRCUIT - Siemens Aktiengesellschaft

Title:

THRESHOLD VALUE LOGIC CIRCUIT

Document Type and Number:

Japanese Patent JP3484331

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To reduce a chip surface area by forming a partial sum signal by the gate electrode of a neuron MOS transistor in a 1st circuit part and controlling another neuron MOS transistor by the partial sum signal in a 2nd circuit part.
SOLUTION: Transistors M1 and M3, and M2 and M4 of a weighting circuit for a cell part CZ form inverters. The inverter composed of the transistors M2 and M4 is connected to a reference potential VSS via a right side branch path in the form of the neuron MOS transistor M6. The floating gate G of the transistor M6 supplies a partial sum signal TS, and its input gate is connected to the input side of bits ai to ci and si. The cell part SZ for forming a sum bit Si+1 has a weighting circuit, which has two input branch paths similarly to the cell part CZ. Then, the partial sum signal TS is supplied to the right side branch path of the cell part SZ by the floating gate G of the n-channel neuron MOS transistor M6.

Inventors:

Andreas look
Laurent Theves
Werner Weber

Application Number:

JP29685297A

Publication Date:

January 06, 2004

Filing Date:

October 29, 1997

Export Citation:

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Assignee:

Siemens Aktiengesellschaft

International Classes:

G06G7/60; G06F7/52; H01L21/8247; H01L27/115; H01L29/78; H01L29/788; H01L29/792; H03K19/20; (IPC1-7): H03K19/20; G06G7/60; H01L21/8247; H01L27/115; H01L29/78; H01L29/788; H01L29/792

Domestic Patent References:

JP11507458A

Other References:

【文献】米国特許4663740(US,A)
【文献】国際公開96/42049(WO,A1)

Attorney, Agent or Firm:

Toshio Yano (2 outside)

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