Title:
Timing control to a mismatching signal receiver
Document Type and Number:
Japanese Patent JP6179836
Kind Code:
B2
Abstract:
A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.
Inventors:
Mozak, Christopher, Pee.
Application Number:
JP2016521920A
Publication Date:
August 16, 2017
Filing Date:
July 01, 2014
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F12/00; G11C11/4076
Domestic Patent References:
| JP2000231421A | ||||
| JP2006277870A | ||||
| JP2011142566A |
Foreign References:
| WO2012082274A1 | ||||
| US20070217559 | ||||
| US20130044845 | ||||
| US6509771 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation
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