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Patent Searching and Data


Title:
PREVENTING SYSTEM FOR INFLUENCE OF FAULT
Document Type and Number:
Japanese Patent JPS5848150
Kind Code:
A
Abstract:

PURPOSE: To prevent the influence of a fault during the execution of a compound instruction without extending arithmetic time by providing a temporary storage means which is set in case of the occurrence of a fault and reset on the completion of an instruction, and a gate means which is turned on and off by the output of said means.

CONSTITUTION: When the cause of an interruption against which operation need be protected is caused and an interruption mask is not set, a flip-flop F/F is set by the output of a gate G0. Once the F/F is set, operation protecting gates G1W G3 are closed by its output. Consequently, an arithmetic indication signal for indicating the contents of arithmeitc to be performed by an arithmetic circuit, a write destination indication signal for indicating a register where an arithmetic result, etc., is to be written, and a control signal for indicating the operation of an external device, etc. which are all some of signals from a register CMIR are inhibited from being transmitted, thus preventing the influence of the fault.


Inventors:
GOUUKON KAZUHIKO
Application Number:
JP14661681A
Publication Date:
March 22, 1983
Filing Date:
September 17, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/00; (IPC1-7): G06F11/00; G06F11/20
Attorney, Agent or Firm:
Kugoro Tamamushi